DEC 1998

Question Paper of CS-12 – Computer Architecture of Dec 1998 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1.(a) Explain in brief how instruction set, compiler technology, cache and memory hierarchy and CPU implementation affect the CPU performance and justify the effects in terms of program length, clock rate and effective CPI (cycles per instruction).

(b) Analyze the data dependence among the following statements in a given program fragment: LoadR1, M[100] / R1 � M[100] / LoadR2, M[104] / R2 � M[104] / MULT R1, R2 / R1 �( R1) x ( R2) / INCR1 / R1 � (R1) + 1 / STORE M[110], R1 / M[110] � (R1) / Also
� Draw a dependence graph to show all the dependences.
� Are there any resources dependence if only one copy of each functional unit is available in the CPU?

(c) Discuss the following terms in the context of the performance of a memory hierarchy.

� Hit ratio
� Memory hierarchy optimization subject to a cost constraint.

2. (a) Explain the difference between superscalar and very long instruction word architecture in term of hardware and software requirements.

(b) Compare the instruction set architecture in RISC and CISC processors in terms of instructions formats, addressing modes and cycles per instruction (CPI)

(c) Compare control flow, dataflow and reduction computers in terms of the program flow mechanism.

3. Define the following basic terms related to modern processor technology:

� Unified versus split caches
� Hardwired versus micro coded control
� Resource conflicts

4. Discuss the cache coherence problem in data sharing and process migration. Also discuss the issue related to snoopy protocol performance.

5. Explain the following concepts with reference to multicomputer networks and message passing mechanism:

� Virtual channel versus physical channel
� Buffer deadlock versus channel deadlock
� Buffering flow control using virtual cut-through routing

6. Describe local and global code optimization with proper examples.

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