JUNE 2002

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Question Paper of CS-12 – Computer Architecture of June 2002 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. (i) Consider the execution of the following code segment. Use Bernstein’s condition to detect the maximum parallelism embedded in this code. Justify the portion that can be executed is parallel and the remaining portion that must be executed sequentially.

S1 : A = B + C
S2 : C = D + E
S3 : F = G + E
S4 : C = A + F
S5 : M = G + G
S6 : A = L + C
S7 : A = E + A

(ii) Draw a dependence graph to show all the dependences for the above code segment.

(iii) Answer the following questions:

(a) Distinguish between single threaded and multithreaded processor architecture.

(b) What difficulties will arise when a computer is scaled to become a-massively parallel processing (MPP) system.

(c) Explain the differences between superscalar and very large instruction word (VLIW) architectures in terms of hardware and s/w requirements.

(d) Describe the advantages and short-comings of daisy-chaining scheme for bus arbitration in a multiprocessor system.

(e) Plot the graph showing the speedup factors and optimal number of pipeline stages for a linear pipeline unit. What are the pros and cons?

2 Explain the following terms:
(a) Private cache vs Shared cache
(b) Ring and chordal rings
(c) Hardwired vs Microcoded control.
(d) Network partitioning for multicasting communication.
(e) HIT ratio.

3. (i) What are the two approaches to interleaved memory organization? What is its significance? Draw a complete eight-way high order interleaving diagram. Also explain what are the major and minor cycles for pipelined access and how these two are related?

(ii) What is the architectural distinction between RISC and CISC processors? Explain the concept of overlapping register windows in the SPARC architecture diagrammatically?

4. Distinguish among the following:

(i) Data flow and reduction computers
(ii) Coarse grain and medium grain level parallelism
(iii) Numeric processing and symbolic processing computers in terms of common operations, memory requirements and processor architecture.

5. Answer the following questions as applied to multiprocessors and multicomputers: [15]

(a) Buffering flow control using virtual cut through routing
(b) Blocking flow control in wormhole routing
(c) Virtual networks and sub networks

6. Answer the following questions:

(i) What is the purpose of prefetch buffers in instruction pipelining?

(ii) What is the cache coherence problem? What are the cache inconsistencies resulting from it? Give a solution to this problem?

(iii) What are the tradeoffs in scalability analysis?

Comment for JUNE 2002
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mca
i want to take admission in MCA
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December, 2001

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Question Paper of CS-12 – Computer Architecture of December 2001 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. (i) What are the design parameters for pipeline processors? Discuss them briefly with examples. 5
(ii) Discuss the structure of superscalar pipelines and the factors causing pipeline stalling. 8
(iii) Consider the execution of an object code with 2,00,000 instructions on a 40 MHz processor. The program consists of four major types of instructions. The instruction mix and the number of cycles (CPI) needed for each instruction type are given below based on the result of a program trace experiment :

Instruction type CPI Instruction Mix
Arithmetic and logic 1 60%
Load/store with catche hit 2 18%
Branch 4 12%
Memory reference with catche miss 8 10%

(a) Calculate the average CPI when the program is executed on a uniprocessor with above trace results.
(b) Calculate the corresponding MIPS rate based on the CPI obtained in part (a)

(iv) What is the architectural distinction between RISC and CISC processors? Explain the concept of overlapping register windows in the SPARC architecture diagrammatically.

2. (a) What are the two approaches to interleaved memory organization? What are its significance? Draw a complete eight-way high order interleaving diagram. Also explain what are the major and minor cycles for pipelined access and how are these two related. 8

(b) Design a four-way sector mapping catche organization and explain its functioning. How is it different from fully associative or set associative catche?

3. Distinguish among the following:
(i) SIMD (Single Instruction and Multiple Data) and
MIMD (Multiple Instruction and Multiple Data)

(ii) Instruction level and Loop level parallelism.
(iii) Binary tree and Fat tree interconnection architectures.
(iv) Write through catches and Write back catches.
(v) Hardware and Software parallelism.

4. Answer the following questions :
(i) Why is synchronous pipeline selected over asynchronous pipeline?
(ii) Compare and contrast between shared and distributed memory.
(iii) Compare and contrast between message passing and address switching?
(iv) Explain the difference between superscalar and VLIW architectures in terms of H/W and S/W requirements.
(v) Main features of logic programming model.

5. Answer the following questions with respect to principles of multithreading and principles of scalable performance.

(a) Discuss the four machine parameters to analyze the performance of multithreaded architecture.

(b) The four switching policies to differentiate multithreaded architectures.

(c) Discuss five challenging areas in supercomputer parallel processing application with computational tasks and expected results.

1. Explain in brief the following as applied to multiprocessors and multicomputers.
a. A hierarichal catche/bus architecture for designing a scalable multiprocessor.
b. Network partitioning for multicast communication.
c. Discard and retransmission flow control.

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JUNE 2001

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Question Paper of CS-12 – Computer Architecture of June 2001 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. (i) Consider a catche (M1) and memory(M2) hierarchy with the following characteristics :
M1 : 16 K words, 50 ns access time
M2 : 1 M words, 400 ns access time

Assume 8 words cache blocks and a set size of 256 words with set associative mapping.

(a) Show the mapping between M2 and M1.
(b) Calculate the effective memory access time with a catche hit ratio of h = 0.95.

(ii) Answer the following questions with reference to processors and memory hierarchy:

(a) Explain the relationship between the integer unit and the floating point unit in most RISC processors with scalar or Superscalar organisation.

(b) Explain the difference between Superscalar and VLIW architectures in terms of H/W and S/W requirements.

(c) What are the design tradeoffs between a large register file and a large D-cache?

(iii) Define five important characteristics of parallel algorithms which are machine implement able.

2. (i) Explain how instruction set, compiler technology, CPU implementation and control, and catche and memory hierarchy affect the CPU performance and justify the effects in terms of program length, clock rate and effective CPI.

(ii)(a) What causes a processor pipeline to be under pipelined?

(b) What are the factors limiting the degree of super scalar design?

3. Explain the following concepts associated with cache and memory architecture:
(a) Low order memory interleaving
(b) Memory bandwidth and Fault tolerance
(c) Write through vs Write-back catches
(d) Physical address cache vs Virtual address cache
(e) Cache flushing policies

4. (i) Discuss the three mechanisms for instruction pipelining.

(ii) Draw the architecture of a vector supercomputer and describe it in brief.

5. Describe the following in context of system interconnection architecture: (i) Ring and Chordal ring
(ii) Hypercube
(iii) Multistage Networks

6. Explain the following concepts related to multivector and SIMD computers:
S-access memory organization
Full-scale vector supercomputers
Vector and scalar balance point
Mini supercomputers
Major challenges in the development of future general purpose supercomputer

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JAN 2001

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Question Paper of CS-12 – Computer Architecture of Jan 2001 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1(i) The execution times (in seconds) of four programs on three computers are given below:

Execution Time (in seconds)
Program Computer A Computer B Computer C
P1 1 10 20
P2 1000 100 40
P3 500 1000 50
P4 100 500 100

Assume that 100,000,000 instructions were executed in each of the four programs. Calculate the MIPS rating of each program on each of the three machines. Based on these ratings. Can you draw a clear conclusion regarding the relative performance of the three computers?

(ii) Answer the following questions:
(a) What causes a processor pipeline to be underpipelined?
(b) What are the factors limiting the degree of superscalar design?
(c) Compare the instruction set architecture in RISC and CISC processors in terms of instruction formats and addressing modes.
(d) Factors affecting cache hit ratio.

2 Compare the relative merits of the three cache memory organizations:

(i) Fully-associative cache
(ii) Set-associative cache
(iii) Sector mapping cache

3. Answer the following questions on designing scalar RISC or Superscalar RISC processors: [15]

(i) Why do most RISC integer units use 32 general-purpose registers?

(ii) What are the design tradeoffs between a large register file and a large D-cache?

(iii) Explain the relationship between the integer unit and floating point unit in most RISC processors with scalar or superscalar organization.

4. Answer the following questions on pipelining and superscalar techniques:

(i) Speed-up factors and the optimal number of pipeline stages for a linear pipeline unit.

(ii) Mechanisms for instruction pipelining. ]

5. Explain the following as applied to multiprocessors and multicomputers:

Buffering flow control using virtual cut through routing
Blocking flow control in warm hole routing
Virtual networks and sub networks

6. Distinguish among the following vector processing machines in terms of architecture and performance range:

(i) Full scale vector supercomputers
(ii) High-end mainframes or near supercomputers
(iii) Minisupercomputers or supercomputing workstations

Categories: CS-12 - Computer Architecture Tags:

DEC 2000

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Question Paper of CS-12 – Computer Architecture of Dec 2000 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. (i) Consider a catch (M1) and memory (M2) hierarchy with the following characteristics: M1: 16 K words, 50 ns access time M2: 1 M words, 400 ns access time Assume eight word catche blocks and a set size of 256 word with set-associative mapping

Show the mapping between M2 and M1
Calculate the effective memory access time with a catch hit ratio of h = 0.95.

(ii) What causes a processor pipeline to be under pipelined?

(iii) What is meant by a hierarchical bus system for multiprocessing system? `

2 Discuss the following the context of parallel languages and compilers:

(i) Parallel code generation
(ii) Parallel flow control
(iii) Parallel arrays

3(i) Describe the important characteristics of parallel algorithms which are machine implementable.

(ii) Discuss the is efficiency concept in the context of the efficiency of a parallel algorithm.

4. Discuss the following in the context of computer architecture:

(i) Distributed Arbitration
(ii) Snoopy bus protocol
(iii) Branch handling in instruction pipeline

5. (i) Discuss the architectural environment for a multithreaded computer model.

(ii) What are the limitations of conventional UNIX for parallel processing systems.

(iii) What is the sector mapping cache? Discuss with the help of an example.

6. Explain the structural and operational difference between register to register and memory to memory architecture in building multipipelined supercompter for vector processing. Comment on the advantages and disadvantages in using SIMD computers as compared with the use of pipelined supercomputer for vector processing.

Categories: CS-12 - Computer Architecture Tags:

JUNE 2000

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Question Paper of CS-12 – Computer Architecture of June 2000 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. A low level memory system has eight virtual pages on a disk to be mapped into 4 page frames in the main memory. A certain program generated the following page trace:
1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0

(a) Show the successive virtual pages residing in the 4 page frames with respect to above page trace using the LRU replacement policy. Compute the hit ratio in the main memory. Assume the page frames are initially empty.

(b) Repeat part (a) for the circular FIFO page replacement policy.

(c) In the following program, all 5 instructions are to be executed in minimum time. Assume that all are integer operands already loaded with working registers. No memory reference is needed for the operand fetch operation. Also all intermediate or final results are written back to working registers without conflicts.

P1 : X (A +B) * (A-B)
P2 : Y (C+D) * (C-D)
P3 : Z X + Y
P4 : A E F
P5 : B (X-F) * A

(i) Use the minimum number of working registers to rewrite the above program using plus, minus, multiplication and divide exclusively. Assume a fixed instruction format with 3 register field: two for sources and one for destination.

(ii) Perform a flow analysis of the assembly language obtained in part (i) to reveal all data dependence with a data dependence graph.

2.(a) Discuss the level of parallelism in program execution and the suitability of parallel computer models at each level.

(b) Characterize the architectural operation of SIMD & MIMD computes. Differentiate between multicomputers and multiprocessors based on their structures, resource sharing and inter-process communication.

3. Answer the following questions with respect to static and dynamic interconnection network.

(a) Compare and comment on static interconnection network characteristics in terms of node degree network diameter and bisection width.

(b) Compare and comment on importance of dynamic interconnection network characteristics in terms of minimum latency for unit data transfer. Writing complexity, connectivity and routing complexity.

4. (a) Discuss the four workload growth pattern, its corresponding efficiency curves and various application models of parallel computers under resource constraints and discuss various tradeoffs.

Workload growth pattern Vs Scalability
Workload Vs Efficiency curves
Workload Vs Memory and I/O bounds
Application model Vs Workload Vs Memory and I/O bounds

(b) Discuss the important characteristics of parallel algorithms which are machine implement able. Also discuss suitability of parallel machines in implementation of these characteristics.

5. Answer the following questions:

(a) Explain the effect of block size, set number, associatively and cache size on the performance of set associative cache organization.

(b) With each cache organization, explain the effects of block mapping policies on the hit ratio issues.

(c) Cache flashing policies.

6. Distinguish among the following vector processing machines in terms of architecture, performance range and cost effectiveness:

(a) Full scale vector supercomputer
(b) High end mainframes or near supercomputers
(c) Mini supercomputers or supercomputer workstations.

Categories: CS-12 - Computer Architecture Tags:

DEC 1999

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Question Paper of CS-12 – Computer Architecture of Dec 1999 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1.(i) Draw a table showing performance factors versus system attributes and explain them.

(ii) A 50 MHz processor was used to execute a benchmark program with the following instruction and clock cycles counts.

Instruction type Instruction count Clock cycles count
Integer Arithmetic 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

Determine the effective CPI, MIPS rate and execution time for this program.

(iii) What cause a processor pipeline to be underpipelined?

(iv) What are the factors limiting the degree of superscalar design?

(v) Illustrate a diagram showing asynchronous bus timing using a four edge handshaking (interlocking ) with variable length signals for different speed devices.

2.(i) Draw a comparison table of Control-flow, Data flow and Reduction computers explaining the following:
Basic definition
Advantages
Disadvantages

(ii) Describe the important characteristics of static connection networks.

3(i) Provide several definitions of scalability. Sketch diagrams for scalability matrices and programmability vs scalability and explain them in detail.

(ii) What are tradeoffs in scalability analysis?

4.(i) Explain the following terms associated with cache design
Write through Vs Write-back catches
Cacheable Vs Non-cacheable data
Private catch Vs Shared cache
Cache flushing policies

(ii) With each cache organization explain the effects of block mapping policies on the hit ratio issues.

5. Discuss the following with proper examples and illustrations as applied to superscalar pipeline design:
Superpipeline structure
Data dependence
Pipeline stalling

6. Explain the following terms associated with Multiprocessors and Multi computers:

Buffer deadlock vs Channel deadlock
Buffer flow control using virtual cut-through routing
Blocking flow control in wormhole routing
Network communication latency
Network partitioning for multicasting communications

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JUNE 1999

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Question Paper of CS-12 – Computer Architecture of June 1999 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1.(a) Compare dynamic connection networks such as bus systems, multistage interconnection networks and crossbar switch networks in terms of the following characteristics:

(i) Bandwidth
(ii) Hardware complexity such as switching, arbitration, wires etc.
(iii) Network latency
(iv) Scalability

(b) Compare and also comment on the static connection networks: Linear Array, Ring, Binary tree, 2D-Mesh in terms of the following characteristic:

Node degree
Network diameter
No. of Links
Bisection width
Symmetry

(c) A 2-Level memory system has 8 virtual pages on a disk to be mapped into 4 page frames (PF) in the main memory. A certain program generated the following page trace: 1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 5, 4

(i) Show the successive virtual pages residing in the 4 page frames with respect to the above page trace using the LRU replacement policy. Compute the hit ratio in the main memory. Assume PFs are initially empty.

(ii) Repeat (i) for the circular FIFO page replacement policy. Compute the hit ratio in the main memory.

2.(a) Discuss the various parallelism levels in programs and their implementation issues from the programmer and compiler designer’s viewpoint.

(b) Analyze techniques namely
(1) Grain packing and scheduling
(2) Static multiprocessor scheduling to minimize communication latency and optimize grain size with appropriate example

3.(a) Define the following with the appropriate formulae:
Clock rate and CPI
MIPS rate
Throughput rate

(b) Distinguish between the following:

Multiprocessors and multicomputers based on their structures, resource sharing and inter processor communication.

NUMA and COMA computers
Single- threaded and multi-threaded processor architecture.
4. (a) List five challenging parallel application areas.
(b) Summarize important characteristics of parallel algorithms which are machine implementable.
(c) Discuss in detail the trade-offs in scalability analysis.
5. Explain the following terms associated with cache design:
(a) Write- through versus Write-back caches
(b) Cacheable vs Noncacheable data
(c) Private caches vs shared caches
(d) Cache flushing policies
(e) Factor affecting cache hit ratio
6. (a) What is VLIW architecture? Explain pipelining in VLIW processors.
(b) Compare and contrast Central Arbitration with Distributed Arbitration.
(c) What is the purpose of prefetch buffers in instruction pipelining?

Categories: CS-12 - Computer Architecture Tags:

DEC 1998

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Question Paper of CS-12 – Computer Architecture of Dec 1998 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1.(a) Explain in brief how instruction set, compiler technology, cache and memory hierarchy and CPU implementation affect the CPU performance and justify the effects in terms of program length, clock rate and effective CPI (cycles per instruction).

(b) Analyze the data dependence among the following statements in a given program fragment: LoadR1, M[100] / R1 � M[100] / LoadR2, M[104] / R2 � M[104] / MULT R1, R2 / R1 �( R1) x ( R2) / INCR1 / R1 � (R1) + 1 / STORE M[110], R1 / M[110] � (R1) / Also
� Draw a dependence graph to show all the dependences.
� Are there any resources dependence if only one copy of each functional unit is available in the CPU?

(c) Discuss the following terms in the context of the performance of a memory hierarchy.

� Hit ratio
� Memory hierarchy optimization subject to a cost constraint.

2. (a) Explain the difference between superscalar and very long instruction word architecture in term of hardware and software requirements.

(b) Compare the instruction set architecture in RISC and CISC processors in terms of instructions formats, addressing modes and cycles per instruction (CPI)

(c) Compare control flow, dataflow and reduction computers in terms of the program flow mechanism.

3. Define the following basic terms related to modern processor technology:

� Unified versus split caches
� Hardwired versus micro coded control
� Resource conflicts

4. Discuss the cache coherence problem in data sharing and process migration. Also discuss the issue related to snoopy protocol performance.

5. Explain the following concepts with reference to multicomputer networks and message passing mechanism:

� Virtual channel versus physical channel
� Buffer deadlock versus channel deadlock
� Buffering flow control using virtual cut-through routing

6. Describe local and global code optimization with proper examples.

Categories: CS-12 - Computer Architecture Tags:

JUNE 1998

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Question Paper of CS-12 – Computer Architecture of June 1998 from IGNOU

Note : Question one is compulsory. Answer any three from the rest.

1. (a) What is superpipelining? How is it different from Superscalar pipeline?

(b) Analyse the data dependence of the statements of the following program:
S1: Load RA, M[20] /RA � M[20] /
S2: Load RB, M[25] /RB � M[25] /
S3: Sub RA, RB /RA � RA- RB /
S4: Mult RA, 5 /RA � RA * 5 /
S5: STORE M[20], RA /M[20] � RA /

Draw the dependence graph for the dependencies.

(c) What are the limitations of conventional UNIX for parallel processing systems?

(d) Compare and contrast the cache Associative and sector caches.

(e) Discuss the architecture environment for a Multi-threaded computer model.

(f) What is m-way memory interleaving? Discuss the c-access memory scheme.

2. Discuss the following terms in the context of computer architecture:
(a) Systolic arrays
(b) Multiprocessing requirements at processor level
(c) Scalability
(d) Cross bar switch
(e) VLIW architecture

3.(a) What are the differences between static and dynamic dataflow Computers?

(b) Compare and contrast the central and distributed bus arbitration schemes.

(c) What is multivector computing? How is it useful for supercomputers?

4. (a) What are the different types of vector instructions? Discuss.

(b) What is meant by Cache-Only Memory Architecture (COMA) model? How is it different from non-uniform-memory-access model?

(c) What is meant by hierarchical bus system for multiprocessing systems?

5. Write short notes on the following in the context of computer architecture:

(i) Multifunctional pipelines
(ii) Monitors
(iii) Multicomputers
(iv) Clock rate, MIPS rate and throughput
(v) Branch handling in instruction pipeline

6. Discuss the following in the context of parallel languages and compilers:
(i) Parallel code generation
(ii) Parallel flow control
(iii) Parallel arrays
(iv) Synchronization and communication features needed in parallel languages
(v) Process management features needed for parallel languages

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